This invention relates to electronic device fabrication processes and associated apparatus. More specifically, the invention relates to chemical vapor deposition and dry etch processes for forming dielectric layers, particularly in high aspect ratio, narrow width recessed features.
It is often necessary in semiconductor processing to fill a high aspect ratio gaps with insulating material. This is the case for shallow trench isolation, inter-metal dielectric layers, passivation layers, etc. As device geometries shrink and thermal budgets are reduced, void-free filling of narrow width, high aspect ratio spaces (e.g., AR>3:1) becomes increasingly difficult due to limitations of existing deposition processes.
Most deposition methods either deposit more material on the upper region than on the lower region of a side-wall or form cusps at the entry of the gap. As a result the top part of a high aspect ratio structure sometimes closes prematurely leaving voids within the gap's lower portions. This problem is exacerbated in small features. Furthermore, as aspect ratios increase, the shape of the gap itself can contribute to the problem. High aspect ratio gaps often exhibit reentrant features, which make gap filling even more difficult. The most problematic reentrant feature is a narrowing at the top of the gap. Thus, the etched side-walls slope inward near the top of the gap. For a given aspect ratio feature, this increases the ratio of gap volume to gap access area seen by the precursor species during deposition. Hence voids and seams become even more likely.
While some specific gap fill processes such as TEOS/ozone SACVD (sub atmospheric chemical vapor deposition) deposited BPSG provide generally good results, such processes are expiring due to incompatibility with the advanced device constraint of a maximum thermal budget of 700° C.
Going forward, the deposition of silicon dioxide assisted by high-density plasma chemical vapor deposition (HDP CVD)—a directional (bottom-up) CVD process—is the method of choice for high aspect ratio gap fill. The method deposits more material at the bottom of a high aspect ratio structure than on its sidewalls. It accomplishes this by directing charged dielectric precursor species downward, to the bottom of the gap. Thus, HDP CVD is not an entirely diffusion-based (isotropic) process.
Nevertheless, some overhang still results at the entry region of the gap to be filled. This results from the non-directional deposition reactions of neutral species in the plasma reactor and from sputtering/redeposition processes. The directional aspect of the deposition process produces some high momentum charged species that sputter away material. The sputtered material tends to redeposit on the sidewalls. Thus, the formation of overhang cannot be totally eliminated and is inherent to the physics and chemistry of the HDP CVD process. Of course, limitations due to overhang formation become ever more severe as the width of the gap to be filled decreases, the aspect ratio increases, and the features become reentrant.
Dielectric deposition is normally a one step process in semiconductor device fabrication. In some gap fill applications, in particular in the case of small features with high aspect ratios, a multi-step deposition/etch back type of process has been used in order to remove overhang and facilitate void-free gap fill. For example, a deposition and etch process utilizing HDP CVD deposition and an aqueous HF dip for the etch back step has been used. However, this requires that the wafers be cycled between the plasma deposition system and the wet etch back system for up to five cycles. This results in a very inefficient and low throughput (e.g., about 3 wafers per hour (wph)) process for the gap fill.
In situ low pressure, high energy ions (HDP) have been used for anisotropic etch back of HDP CVD deposited dielectric material in order to keep the top of the structures from closing before the gap (trench) is filled. Such in situ HDP CVD deposition and etch back processes are described, for example, in U.S. Pat. Nos. 6,335,261 and 6,030,881.
While these multi-step deposition and etch back processes have improved high aspect ratio gap fill capabilities, dielectric deposition processes that can fill high aspect ratio features of narrow width, particularly very small features (e.g., about 0.1 um gap width) with aspect ratios of about 6:1 or more, without leaving voids, continue to be sought.